What would you do with this 16.8 million core graphics processing monster?

Should you take a look at it now, particularly with the arrival of massively parallel computing on GPUs, the techs at Tera Computing after which Cray most likely had the correct concept with their massively threaded processors and high-bandwidth interconnects.

On condition that many neural networks created by AI frameworks are themselves graphs – the varieties with vertices with information and edges displaying relationships between information, not one thing created in Excel – or the output quantities to a graph, maybe , ultimately, what we’d like is a very good graphics processor. Or possibly hundreds of thousands of them.

Gasp! Who would converse of such heresy in a world the place the Nvidia GPU and its wannabes are a common salve to be solved – ointment, definitely? – Our trendy computing issues? Properly, we do. Whereas GPUs excel on the dense matrix and high-precision floating-point arithmetic that dominate HPC simulation and modeling, a lot of the information that powers AI frameworks is sparse and fewer exact to run. Given this, there could also be higher methods to do that.

The U.S. Division of Protection’s Superior Analysis Tasks Company, the analysis and growth arm of the Division of Protection, has been exploring such evolving questions and trying to construct massively parallel graphics processor and interconnection because the institution of the Hierarchy of Exploit Verification (HIVE) undertaking again in 2017. HIVE processor producer Intel, MIT’s Lincoln Lab, and Amazon Net Companies have been chosen to create and host a trillion-edge graph dataset for a system primarily based on such chewable processors.

At Scorching Chips 2023 this week, Intel was displaying off the processor it constructed for the HIVE undertaking, initially codenamed “Puma” after the Programmable Built-in Reminiscence Structure (PIUMA) it helps. In August 2019, Intel offered an replace of the PIUMA chip at DARPA’s ERI Summit, and at IEEE’s Excessive Efficiency Excessive Computing 2020 occasion in September 2020, Intel researchers Balasubramanian Sechasai, Joshua Freeman, and Ibrahim Hore gave a presentation titled Hash desk scalability on Intel PUIMAwhich is behind the IEEE paywall however supplies an summary of the processor, and a paper referred to as PIOMA: Programmable Built-in Unified Reminiscence Structure, which isn’t behind a paywall. These have been obscure in regards to the structure of the PIUMA system. However this week, Jason Howard, Principal Engineer at Intel, gave an replace on the PIUMA processor and system, together with the optical interface that Intel in-built collaboration with Ayar Labs to attach an enormous variety of processors collectively.

Within the IEEE paper, the PIUMA researchers didn’t disclose the truth that they have been utterly impressed by the Cray XMT line. The XMT line a decade in the past peaked with an enormous monster of shared reminiscence that was best for chart evaluation, which had as much as 8,192 processors, every with 128 threads operating at 500MHz, plugged into an AMD Rev F socket that… It makes use of Opteron 8000 sequence X86 CPUs mixed with a customized “SeaStar2+” cross-connect that gives 1.05 million threads and 512TB of shared major reminiscence for the graph to stretch its legs on. And so far as Linux was involved, this appeared like a single CPU.

The outdated is the brand new once more with Venture PIUMA, this time the processor is extra modest however the interconnection is significantly better. Presumably so will the value/efficiency, and for the love of all that is holy in heaven, possibly Intel will market this PIOMA and really Shake issues up.

Taking smaller bytes out of reminiscence

When Intel started designing the PIUMA chip, based on Howard, researchers engaged on the HIVE undertaking realized that graph features weren’t solely extremely parallel, however embarrassingly parallel, which meant that there is likely to be some methods to take advantage of this parallelism to boost the efficiency stage of graph analytics. graphic. When operating on customary operating. Having heaps and plenty of branches within the instruction stream put strain on the CPU pipelines and the reminiscence subsystem additionally had plenty of strain on it from lengthy chains of dependent hundreds, destroying the caches on the CPUs.

The PUIMA chip has some massive and small concepts constructed into it, it has 4 pipelines with 16 threads every (referred to as MTPs) and two pipelines with 1 thread every (referred to as STPs) that ship 8x the efficiency of one of many threads inside Medium time period plans. The cores depend on a customized RISC instruction set, which neither Howard recognized nor did his fellow researchers at Intel or Microsoft, which additionally had a hand within the PIOMA effort.

“All pipelines use a devoted ISA, which is analogous to RISC, and is fixed-length,” Howard defined in his Scorching Chips presentation. “And every pipeline has 32 bodily data out there to it. We did this so you may simply migrate computation threads between any of the pipelines. So possibly I am going to begin executing on one of many multi-threaded pipelines and if I see it is taking too lengthy, or possibly It is the final out there thread, so I can rapidly migrate that to my very own single thread for higher efficiency.

The STP and MTP modules are linked by a crossbar, include 192KB of L1 directions and an L1 information cache, and are linked to a shared 4MB SRAM that’s less complicated than the L2 cache.

Every PIUMA chip accommodates eight lively cores, and every core has its personal devoted DDR5 reminiscence controller which has an entry precision of 8 bytes as an alternative of the 72 bytes like common DDR5 reminiscence controllers. Every socket accommodates 32GB of devoted DDR5-4400 reminiscence.

Every core has a pair of routers that join the cores in a 2D community to one another, to eight reminiscence controllers, and to 4 high-speed Superior Interface Bus (AIB) ports. The AIB is a royalty-free PHY for interconnecting chipsets that Intel introduced again in 2018. There are 32 optical I/O ports, eight per AIB, which come from Ayar Labs’ personal die complement, offering 32 GB/s of Bandwidth per port. path.

This is an in depth take a look at the on-chip routers that implement 2D networking on the PUIMA package deal:

This can be a ten-port router, the 2D community runs at 1 GHz and takes 4 cycles to traverse the router. It has ten digital channels and 4 completely different lessons of messages, which Howard says avoids any deadlocks on the community and produces 64 Gbps per hyperlink inside the router.

The router and primary packaging on the PIOMA chip are a bit extra complicated than you would possibly count on. have a look:

It is like there are sixteen cores/routers on the die, and solely eight of them have the cores activated as a result of the community on the die wants twice as many routers to feed into the AIBs, which in flip feed the Ayar Labs photonics silicon. Silicon photonics interconnects are used solely as a bodily layer, and are particularly used to increase the community on the die between a number of sockets.

And after we say a number of, we imply Freaking large quantity. like him:

A sled of sixteen PIOMA chips will be linked utilizing silicon photonics hyperlinks collectively in a 4×4 grid in an all-in-one configuration. Every PIOMA chip burns about 75 watts at nominal voltage and workloads, which implies it burns about 1200 watts. A couple of Xeon SP socket, however not more than three of them.

Construct the right graph processing monster

The PUMA chip has 1 Tbps of optical interconnect popping out of it, and aside from the hyperlinks on the sleds, a few of it may be used to attach as much as 131,072 sleds collectively to create an enormous supercomputer for shared reminiscence graph processing. The routers are the community, and all the things is linked by a HyperX chassis outdoors of the all-to-all chassis linked straight inside a rack containing sixteen chutes.

Let’s stroll by means of this. A single sixteen-socket slide has 128 cores, 8448 threads and 512 GB of reminiscence. The primary stage of the HyperX community has 256 spools, 32,768 cores, 270,336 threads, and 1 TB of reminiscence. Step as much as the second layer of the HyperX community, and you may create a PIOMA cluster with 16,384 chips, 2.1 million cores, 17.3 million threads, and 64TB of shared reminiscence. Lastly, at Stage 3 of the HyperX community, you may broaden to 131,072 slices, 16.8 million cores, 138.4 million threads, and 512 petabytes of shared reminiscence.

I admit it. Need to see what certainly one of these monsters can do? The US Nationwide Safety Company, the US Division of Protection and their friends world wide, who’ve funded a lot AI analysis prior to now 15 years, are additionally undoubtedly .

Whilst you’re chewing by means of this scale for a minute, let’s get to a couple different issues. First, the latency of that optical community:

The PUMA nodes are interconnected with single-mode optical fiber, and curiously, the bandwidth achieved for the PUMA community design, at 16 Gb/s per path, was solely the theoretical design level. However even then, this can be a large bandwidth beast, with a theoretical bandwidth of 16 petabit/s of unidirectional segmented bandwidth throughout your complete HyperX community.

The PUIMA chip is carried out in Taiwan Semiconductor Manufacturing Co.’s 7nm FinFET processes, and accommodates 27.6 billion transistors, of which 1.2 billion are devoted to comparatively small cores. AIB circuits appear to take up plenty of transistors.

This is what the PIUMA chipset package deal appears to be like like:

This is what the package deal and check boards seem like:

Up to now, Intel has constructed two boards every containing a single PIUMA chip and linked them collectively to conduct its assessments and exhibit its success to DARPA.

The query now could be: How a lot does this machine value on a big scale? Properly, at $750 per node, which is not so much in any respect, that is $3.1 million for a system stretched to the first stage of HyperX with 4,096 PIOMA chips, and virtually $200 million for a single system with 262,144 chips on the 2nd stage of HyperX, 1 $57 billion for one with 2.1 million chips prolonged to HyperX Stage 3.

Because the generative explosion of AI reveals, there are dozens of corporations, after which dozens of different authorities businesses on this planet that will not even blink at a billion {dollars} for a system anymore. The quantity did not even increase my pulse once I wrote it down after which learn it.

That is the time we reside in now.

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